1. Field of the Invention
This invention relates to electronic circuits, and more particularly, to pulse generating circuits.
2. Description of the Related Art
Pulse generating circuits are well known in the art of electronics. Pulse generators may be defined by such factors as pulse repetition rate (i.e. frequency), pulse width, trigger delay, duty cycle, rise and fall times, and voltage levels (i.e. of high and low signals).
FIG. 1A is a schematic diagram of one embodiment of a pulse generator circuit. In the embodiment shown, pulse generator 10 includes a NAND gate and an odd number of inverters coupled in series to form a delay chain. A clock input (‘clk’) is provided directly to one of the inputs of the NAND gate, and is also input into the delay chain. When the input clock signal and the delayed clock signal are both high, the output of the NAND gate will fall low. The low from the NAND gate may be provided to a clock header having an odd number of inversions to produce a high pulse that has substantially the same width as the low pulse from the NAND gate.
FIG. 1B is a schematic diagram of an alternate embodiment of a pulse generator. In this embodiment, pulse generator 20 includes a delay chain having only 5 inverters (instead of 13, as in the example of FIG. 1A). However, each of the inverters includes two PMOS devices and two NMOS devices, as shown, in contrast to typical inverters that include only one each of a PMOS and NMOS device. Such an inverter configuration may provide a higher input capacitance and lower drive may thus generate delay more efficiently than the typical inverter configuration having only one PMOS device and one NMOS device.
Thus, variations of either of the embodiments discussed above may be used to construct pulse generators. Factors such as desired pulse width may determine the number of inverters used in constructing the pulse generator circuit. If delay efficiency is a design priority, the inverters of the type shown in FIG. 1B may be used in lieu of the standard inverter type used in FIG. 1A.
In implementing the pulse generators discussed above, device size (and more specifically, channel width of the transistors used) is one factor to be considered in the design. Pulse generators may be implemented with smaller devices when it is desirable to minimize power consumption. However, smaller devices are more subject to process variation during manufacturing. Accordingly, variations from one pulse generator to another, when implemented using small devices, may result in a corresponding variation in pulse widths from one pulse generator to another. Since such variations tend to be averaged out in larger devices, the use of such large devices may enable the manufacture of pulse generators having more uniform characteristics from one to another. However, larger devices typically consume more power than their smaller counterparts.